1. Field of the Invention
The present invention relates to an array substrate for a liquid crystal display (LCD), and a method for manufacturing thereof.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) shows an image by using the electro-optical characteristics of a liquid crystal layer. The LCD includes a color filter substrate and an array substrate arranged opposite each other with a liquid crystal layer interposed between them. The array substrate uses a thin film transistor (TFT) as a switching device. The array substrate will be described in detail with reference to FIGS. 1 and 2.
FIG. 1 is a plan view showing an array substrate for an LCD according to the related art. FIG. 2 is a cross-sectional view showing the array substrate of FIG. 1 along a line I-I′.
Referring to FIGS. 1 and 2, the array substrate 1 for an LCD comprises gate lines 20, data lines 30, thin film transistors 40, pixel electrodes 50, common electrodes 52, common lines 54, and storage electrodes 60.
The gate lines 20 and the data lines 30 are formed to be insulated from and to cross each other on a transparent substrate 10 with a gate insulation layer 32 between them to thereby define pixel regions.
The thin film transistors 40 are connected to the gate lines 20 and the data lines 30 and used as switching devices. To be used as a switching device, each thin film transistor 40 comprises a gate electrode 41, a source electrode 42, a drain electrode 43, an active layer 44, and an ohmic contact layer 45.
Each pixel electrode 50 forms an electric field together with a common electrode 52 by using a data voltage supplied from the drain electrode 43. For this, the pixel electrode 50 is connected to the drain electrode 43 through a contact hole 72 that penetrates an inorganic insulation layer 70.
Also, each common electrode 52 forms an electric field together with the pixel electrode 50 by using a common voltage supplied from a common line 54. For this, the common electrode 52 extends from the common line 54 to which it pertains and formed to be crossed with a pixel electrode 50. Also, the common electrodes 52 are formed of the same material as that of the gate lines 20 and the gate electrodes 41 on the same plane. Herein, the electric field is formed by a voltage difference between the common voltage and the data voltage.
The common lines 54 provide the common electrodes 52 with a common voltage supplied from the outside. To provide the common voltage, the common lines 54 are formed of the same material as that of the gate lines 20 and the gate electrodes 41 on the same plane.
The storage electrodes 60 maintain the data voltage of the pixel electrodes 50 at a level higher than a predetermined value. In short, the storage electrodes 60 maintain the data voltage of the pixel electrodes 50 at a uniform level for one frame in the LCD comprising the array substrate 1. To maintain the data voltage, the storage electrodes 60 are connected to the pixel electrodes 50 through the contact holes 74 penetrating the inorganic insulation layer 70 and they are formed as large as possible.
The storage electrodes 60 are insulated from and overlap the common lines 54 with a gate insulation layer 32 interposed between them. Herein, storage capacitances (Cst) are formed at places where the storage electrodes 60, the common lines 54 and the gate insulation layer 32 are overlapped.
In the related art, when the pixel electrodes 50 and the data lines 30 are formed in the array substrate 1 for the LCD, overlay deviation may occur between the pixel electrodes 50 and the data lines 30.
Therefore, there is a problem that the value of parasitic capacitance (Cdp) formed between the pixel electrode 50 and the data line 30 may differ according to each pixel area. The different parasitic capacitance values deteriorate the image quality of the LCD comprising the array substrate 1.
Also, there is a problem that the common lines 54 and the gate lines 20 should be spaced apart from each other by a predetermined space to prevent shorts from occurring between the gate lines 20 and the common lines 54. In addition, the common lines 54 should be formed wide to form the storage capacitance (Cst). Therefore, there is a problem that the LCD comprising the array substrate 1 has a decreased aperture ratio.